FPL=FPL_0, PMIC_DELAY_SCALER=PMIC_DELAY_SCALER_0, SYS_MEM_DS_CTRL=SYS_MEM_DS_CTRL_0, INT_MEM_CLK_LPM=INT_MEM_CLK_LPM_0, EFUSE_PROG_SUPPLY_GATE=EFUSE_PROG_SUPPLY_GATE_0
CCM General Purpose Register
| PMIC_DELAY_SCALER | Defines clock dividion of clock for stby_count (pmic delay counter) 0 (PMIC_DELAY_SCALER_0): clock is not divided 1 (PMIC_DELAY_SCALER_1): clock is divided /8 |
| EFUSE_PROG_SUPPLY_GATE | Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing 0 (EFUSE_PROG_SUPPLY_GATE_0): fuse programing supply voltage is gated off to the efuse module 1 (EFUSE_PROG_SUPPLY_GATE_1): allow fuse programing. |
| SYS_MEM_DS_CTRL | System memory DS control 0 (SYS_MEM_DS_CTRL_0): Disable memory DS mode always 1 (SYS_MEM_DS_CTRL_1): Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled 2 (SYS_MEM_DS_CTRL_2): enable memory (outside ARM platform) DS mode when system is in STOP mode |
| FPL | Fast PLL enable. 0 (FPL_0): Engage PLL enable default way. 1 (FPL_1): Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. |
| INT_MEM_CLK_LPM | Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal 0 (INT_MEM_CLK_LPM_0): Disable the clock to the ARM platform memories when entering Low Power Mode 1 (INT_MEM_CLK_LPM_1): Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) |